The present invention relates to a gray scale mask, and particularly, to a gray scale mask used for forming the source/drain layer (S/D layer) of a thin film transistor (TFT).
Currently, in a manufacturing process of a liquid crystal display (LCD) panel, it is needed to repeat thin film deposition, photolithography with a mask, and etching for several times to manufacture an array substrate and a color filter substrate. The array substrate includes a TFT as a switching element for each pixel. A five-mask (5Mask) technology is commonly used to form an array substrate comprising TFTs. With the progress of the manufacturing process, some manufacturers have attempted to employ a four-mask (4Mask) technology. The 4Mask process reduces one masking process compared with the conventional 5Mask process and shortens the process period with low cost. Therefore, the 4Mask process is becoming the mainstream for manufacturing a TFT LCD array substrate.
In the 4Mask process, the masking processes for forming an active layer and for forming a source/drain layer in the 5Mask process are combined into a single one. In the 4Mask process, a gray scale photoresist pattern is formed with a mask having combination of slits and light-blocking bars, and the channel of a TFT is formed by performing two etching processes. FIG. 9 shows a conventional gray scale mask used for the exposure process for forming the source/drain layer. On the gray scale mask, there are provided a source mask region 20 for forming the source of a TFT and a drain mask region 10 for forming the drain of the TFT. An end of the source mask region 20 is located within the drain mask region 10 of U-shape, so that a U-shaped channel region is formed in the TFT after photolithography and etching. As shown in FIG. 9, on the gray scale mask, a light-blocking bar 60 is arranged along the extending direction of the channel in the region where the channel region is to form. Slits 50′ are formed between the light-blocking bar 60 and the source mask region 20 and between the light-blocking bar 60 and the drain mask region 10, respectively. Due to the generated double-slit interference, after exposure and development, a gray scale photoresist pattern is obtained, of which a relatively flat gray scale photoresist portion (i.e., a photoresist portion whose height is in proportion to that of the photoresist portions for the source/drain, and the ratio of height between the portions is for example 1/2) is formed in the region where the channel region is to form. With the gray scale mask pattern, a first etching is performed to obtain a source/drain pattern, and after ashing on the photoresist pattern, a second etching can be performed to obtain the desired channel.
However, when an exposure process is performed for the source/drain layer with the mask in which the light-blocking bar is arranged along the U-shaped channel region, the intensity of light obtained with the double-slit interference is shown in FIG. 10. In this case, although a gray scale photoresist pattern is obtained, non-uniform thickness of the photoresist may be generated in a corner portion, central portion, and/or edge portion of the U-shaped channel region due to the non-uniform intensity of the light passing through the slits and may cause projections at the surface of the above portions of the photoresist pattern. These projections may give rise to residues of the active layer or short circuit in the source/drain layer in the channel of the TFT after etching with the gray scale photoresist pattern.